Name
Abstract | ||
|---|---|---|
In this paper, we present a new algorithm for the statistical static timing analysis of a CMOS combinatorial circuit, which can treat correlations of arrival times of input signals to a logic gate and correlations of switching delays in a logic gate. We model each switching delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the distribution of output delay of a logic gate. Since the algorithm takes the correlation into account, the time complexity is O(n*m) in the worst-case, where n and m are the numbers of vertices and edges of the acyclic graph representing a given combinatorial circuit. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1145/370155.370390 | ASP-DAC |
Keywords | Field | DocType |
CMOS logic circuits,circuit complexity,combinational circuits,delays,graph theory,logic CAD,logic gates,statistical analysis,timing,CMOS combinatorial circuit,acyclic graph,arrival times,delay correlations,edges,input signals,logic gate,normal distribution,statistical static timing analysis,stochastic variables,switching delays,time complexity,vertices | Delay calculation,Normal distribution,Logic gate,Statistical static timing analysis,Circuit complexity,Electronic engineering,Real-time computing,Directed acyclic graph,Combinational logic,Time complexity,Mathematics | Conference |
ISBN | Citations | PageRank |
0-7803-6634-4 | 17 | 2.80 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shuji Tsukiyama | 1 | 85 | 19.66 |
| Masakazu Tanaka | 2 | 17 | 2.80 |
| Masahiro Fukui | 3 | 42 | 14.57 |