Name
Abstract | ||
|---|---|---|
This Parameterized Digital Electronic Arithmetic (PDEA) model replaces linear operations with non-linear ones. In this paper we introduce a hardware implementation of the parametric image-processing framework that will accurately process images and speed up computation for addition, subtraction, and multiplication. Particularly, the paper presents the design of arithmetic circuits including parallel counters, adders and multipliers based in two high performance threshold logic gate implementations that we have developed. We will also explore new microprocessor architectures to take advantage of arithmetic. The experiments executed have shown that the algorithm provides faster and better enhancements from those described in the literature. Its potential applications include computer graphics, digital signal processing and other multimedia applications. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ICSMC.2009.5346740 | SMC |
Keywords | Field | DocType |
adders,counting circuits,digital arithmetic,digital signal processing chips,image processing,logic gates,multiplying circuits,threshold logic,adders,arithmetic circuits,computer graphics,digital signal processing,microprocessor architectures,multimedia applications,multipliers,parallel counters,parameterized digital electronic arithmetic model,parametric image-processing framework,threshold logic gate implementations,Digital Electronic Arithmetic,Implementation of Logarithmic Image Processing Operations,Logarithmic Number System | Digital signal processing,Adder,Computer science,Arbitrary-precision arithmetic,Microprocessor,Arithmetic,Field-programmable gate array,Multiplication,Logarithmic number system,Saturation arithmetic | Conference |
ISSN | Citations | PageRank |
1062-922X | 0 | 0.34 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Khader Mohammad | 1 | 13 | 5.22 |
| Sos Agaian | 2 | 67 | 16.48 |
| Fred Hudson | 3 | 0 | 0.34 |