Name
Abstract | ||
|---|---|---|
The development and implementation of an algorithm that forms the basis of a very-high-speed integrated circuit hardware description language (VHDL) fault diagnosis tool (VFDT) are discussed. Given a VHDL description, a compiler creates an internal representation suitable for simulation and fault diagnosis. VFDT diagnoses faults in this representation hierarchically using the stuck-at fault model at the first level and the arbitrary-failure model at the second level. It reasons from first principles by means of constraint suspension. Examples of fault diagnosis using the VFDT are described. |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/54.143144 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
VLSI,circuit layout CAD,fault location,specification languages,VHDL fault diagnosis tool,arbitrary-failure model,compiler,functional fault models,simulation,stuck-at fault model,very-high-speed integrated circuit hardware description language | Algorithm design,Sequential logic,Computer science,Compiler,Electronic engineering,Network analysis,VHDL,Computer engineering,Very-large-scale integration,Fault model,Hardware description language | Journal |
Volume | Issue | ISSN |
9 | 2 | 0740-7475 |
Citations | PageRank | References |
2 | 0.40 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vijay Pitchumani | 1 | 125 | 21.38 |
| Pankaj Mayor | 2 | 9 | 1.30 |
| Nimish Radia | 3 | 20 | 2.86 |