Name
Title | ||
|---|---|---|
A platform-based SoC design and implementation of scalable automaton matching for deep packet inspection |
Abstract | ||
|---|---|---|
String matching plays a central role in packet inspection applications such as intrusion detection, anti-virus, anti-spam and Web filtering. Since they are computation and memory intensive, software matching algorithms are insufficient to meet the high-speed performance. Thus, offloading packet inspection to a dedicated hardware seems inevitable. This paper presents a scalable automaton matching (SAM) coprocessor that uses Aho-Corasick (AC) algorithm with two parallel acceleration techniques, root-indexing and pre-hashing. The root-indexing can match multiple bytes in one single matching, and the pre-hashing can be used to avoid bitmap AC matching which is a cycle-consuming operation. In the platform-based SoC implementation of the Xilinx ML310 FPGA, the proposed hardware architecture can achieve almost 10.7Gbps and support over 10,000 patterns for virus, which is the largest pattern set from among the existing works. On the average, the performance of SAM is 7.65 times faster than the original bitmap AC. Furthermore, SAM is feasible for either internal or external memory architecture. The internal memory architecture provides high performance, while the external memory architecture provides high scalability in term of the number of patterns. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1016/j.sysarc.2007.03.005 | Journal of Systems Architecture |
Keywords | Field | DocType |
high-speed performance,single matching,dedicated hardware,content filtering,string matching,automaton,bitmap ac matching,internal memory architecture,deep packet inspection,platform-based soc design,high performance,external memory architecture,scalable automaton matching,proposed hardware architecture,external memory,indexation,hardware architecture,aho corasick,intrusion detection | String searching algorithm,Deep packet inspection,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Bitmap,Coprocessor,Auxiliary memory,Embedded system,Hardware architecture,Scalability | Journal |
Volume | Issue | ISSN |
53 | 12 | Journal of Systems Architecture |
Citations | PageRank | References |
7 | 0.53 | 19 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ying-Dar Lin | 1 | 899 | 116.04 |
| Kuo-Kun Tseng | 2 | 19 | 2.13 |
| Tsern-Huei Lee | 3 | 244 | 30.63 |
| Yi-Neng Lin | 4 | 47 | 5.78 |
| Chen-Chou Hung | 5 | 8 | 0.88 |
| Yuan-Cheng Lai | 6 | 761 | 73.52 |