Name
Abstract | ||
|---|---|---|
This paper describes a slight-boost scheme to improve a transistor performance in system large-scale integrated circuits, which integrate logic circuits and 1-Tr/1-C DRAMs. In this scheme, an embedded SDRAM core has been developed for graphic and multimedia applications. Its maximum operating frequency is 166 MHz, with a peak data rate of 5.3 GB/s. As well, a fast row-address access time of 22 ns ... |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/4.760377 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
SDRAM,MOSFETs,Voltage,Random access memory,Circuit testing,Large scale integration,Logic circuits,Graphics,Frequency,Logic design | Journal | 34 |
Issue | ISSN | Citations |
5 | 0018-9200 | 0 |
PageRank | References | Authors |
0.34 | 1 | 12 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Yamazaki | 1 | 6 | 3.46 |
| T. Yamagata | 2 | 0 | 0.34 |
| M. Hatakenaka | 3 | 0 | 0.34 |
| A. Miyanishi | 4 | 0 | 0.34 |
| I. Hayashi | 5 | 0 | 0.34 |
| S. Tomishima | 6 | 1 | 0.82 |
| A. Mangyo | 7 | 0 | 0.34 |
| Y. Yukinari | 8 | 13 | 4.23 |
| T. Tatsumi | 9 | 0 | 0.34 |
| M. Matsumura | 10 | 0 | 0.34 |
| K. Arimoto | 11 | 0 | 0.34 |
| M. Yamada | 12 | 0 | 0.34 |