Title
Computation of Bus Current Variance for Reliability Estimation of VLSI Circuits
Abstract
Abstract This paper deals with the estimation of the median time-to-failure (MTF) due to elec-tromigration in the power and ground busses of CMOS VLSI circuits. In our previous work [3, 4], we presented a novel technique for MTF estimation based on a stochastic cur-rent waveform model. In [6], we argued that including the variance waveform of the current, in addition to its expected waveform derived in [3, 4], would further improve the accuracy of the MTF estimate. In this paper, we present a novel technique for deriving the variance waveform for CMOS circuits. Using this technique, we establish the importance of the vari-ance waveform by showing that its contribution to the MTF estimate can be in the range of 100% to 200% relative to that of the expected waveform. The technique has been built into the probabilistic simulator CREST [3, 4], and has shown good agreement with SPICE, as well as excellent speedup.
Year
DOI
Venue
1989
10.1109/ICCAD.1989.76936
ICCAD
Field
DocType
Citations 
Computer science,Spice,Waveform,Real-time computing,CMOS,Electronic engineering,Probabilistic logic,Electronic circuit,Very-large-scale integration,Speedup,Computation
Conference
2
PageRank 
References 
Authors
0.48
4
3
Name
Order
Citations
PageRank
F. N. Najm12097571.66
Ibrahim Hajj2749.03
Ping Yang3407200.75