Title
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
Abstract
This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over 3" FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 1.6-Gbps and 6.4-Gbps operations, respectively, without package change. The compact, low-power and h...
Year
DOI
Venue
2012
10.1109/JSSC.2012.2185370
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
Clocks,Multiplexing,Phase locked loops,Delay,Random access memory,Receivers,Generators
Electrical efficiency,Transmitter,Phase-locked loop,Intersymbol interference,Equalization (audio),Computer science,Electronic engineering,Multiplexing,Data link,Low-power electronics
Journal
Volume
Issue
ISSN
47
4
0018-9200
Citations 
PageRank 
References 
2
0.38
0
Authors
34