Paper Info
Title
A Wide Output Range, Mismatch Tolerant Sigma Delta Dac For Digital Pll In 90nm Cmos
Abstract
A mismatch-tolerant current-mode Sigma Delta (Sigma Delta) Digital to Analog Converter (DAC) is presented here. The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought out for separate Sigma Delta operation. This increases the DAC range even as the Sigma Delta step size and range are kept small to minimize Sigma Delta switching noise. Mismatch between DAC current elements can result in Differential Non Linearity (DNL) at the DAC output. A novel scheme is proposed to mitigate this effect. It involves skewing the thresholds of the quantizer in the Sigma Delta modulator based on the DAC input, in order to control which DAC elements are used in generating a particular output current. The DAC, implemented as part of a Digital PLL in 90nm CMOS, yields a current range of up to 2mA and occupies an area of 0.035mm(2). It is shown that the proposed scheme attenuates mismatch effects by a factor of 16.
Year
DOI
Venue
2012
10.1109/ISCAS.2012.6272127
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)
Keywords
Field
DocType
quantizer,differential nonlinearity,switches,quantization,cmos integrated circuits,sigma delta modulator,noise,cmos,phase locked loops,modulation
Integral nonlinearity,Phase-locked loop,Differential nonlinearity,Control theory,Computer science,Modulation,Delta-sigma modulation,Electronic engineering,CMOS,Digital-to-analog converter,Quantization (signal processing),Electrical engineering
Conference
ISSN
Citations 
PageRank 
0271-4302
0
0.34
References 
Authors
0
2
Name
Order
Citations
PageRank
Anant S. Kamath163.06
Biman Chattopadhyay293.57