Name
Title | ||
|---|---|---|
Multiplierless Approximate 4-point DCT VLSI Architectures for Transform Block Coding. |
Abstract | ||
|---|---|---|
Two multiplierless algorithms are proposed for 4x4 approximate-DCT for transform coding in digital video. Computational architectures for 1-D/2-D realisations are implemented using Xilinx FPGA devices. CMOS synthesis at the 45 nm node indicate real-time operation at 1 GHz yielding 4x4 block rates of 125 MHz at less than 120 mW of dynamic power consumption. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1049/el.2013.1352 | Electronics Letters |
Keywords | Field | DocType |
CMOS integrated circuits,discrete cosine transforms,field programmable gate arrays,power consumption,transform coding,video coding,frequency 1 GHz,power 120 mW,frequency 125 MHz,dynamic power consumption,CMOS synthesis,Xilinx field programmable gate array devices,computational architectures,digital video,transform coding,4A4 approximate-discrete cosine transform,multiplierless algorithms,transform block coding,multiplierless approximate 4-point DCT VLSI architectures | Digital video,Block code,Discrete cosine transform,Field-programmable gate array,Transform coding,Electronic engineering,CMOS,Dynamic demand,Very-large-scale integration,Mathematics | Journal |
Volume | Issue | ISSN |
abs/1405.0413 | 24 | Electronics Letters, vol. 49, no. 24, pp. 1532-1534, 2013 |
Citations | PageRank | References |
6 | 0.48 | 2 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fábio M. Bayer | 1 | 126 | 12.89 |
| Renato J. Cintra | 2 | 218 | 26.82 |
| Arjuna Madanayake | 3 | 242 | 53.31 |
| U. S. Potluri | 4 | 12 | 1.28 |