Name
Abstract | ||
|---|---|---|
H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real-time applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained to be employed. The hardware utilization and throughput are also decreased because of the block/MB/frame-level reconstruction loops. In this paper, we describe our techniques to design the H.264/AVC video encoder for HDTV applications. On the system design level, in consideration of the characteristics of the key components and the reconstruction loops, the four-stage macroblock pipelined system architecture is first proposed with an efficient scheduling and memory hierarchy. On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional motion estimation, reconfigurable intrapredictor generator, dual-buffer block-pipelined entropy coder, and deblocking filter. With these techniques, the prototype chip of the efficient H.264/AVC encoder is implemented with 922.8 K logic gates and 34.72-KB SRAM at 108-MHz operation frequency. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TCSVT.2006.873163 | IEEE Trans. Circuits Syst. Video Techn. |
Keywords | Field | DocType |
parallel processing,pipelining processing techniques,single-chip video encoder,parallel processing techniques,joint video team (jvt),efficient scheduling,avc encoder,integer motion estimation,module design level,reconfigurable intrapredictor generator,system design level,four-stage macroblock pipelined system,motion estimation,h.264/avc encoder,computational complexity,efficient h.264,dual-buffer block-pipelined entropy coder,frame-level reconstruction loop,video coding,avc video encoder,iso/iec 14496-10 avc,high definition television,filtering theory,hardwired encoder,deblocking filter,very large-scale integration (vlsi) architecture,code standards,architecture design,design consideration,itu-t rec. h.264,entropy codes,hdtv720p,video coding standards,pipeline processing,logic gate,indexing terms,system design,hardware architecture,system architecture,chip,throughput,hardware,computer architecture | Computer science,Context-adaptive variable-length coding,Systems design,Artificial intelligence,Computer hardware,Deblocking filter,Context-adaptive binary arithmetic coding,Scalable Video Coding,Macroblock,Computer vision,Memory hierarchy,Encoder,Embedded system | Journal |
Volume | Issue | ISSN |
16 | 6 | 1051-8215 |
Citations | PageRank | References |
102 | 5.89 | 22 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tung-Chien Chen | 1 | 791 | 78.22 |
| Shao-Yi Chien | 2 | 1603 | 154.48 |
| Yu-Wen Huang | 3 | 1116 | 114.02 |
| Chen-Han Tsai | 4 | 185 | 13.75 |
| Ching-Yeh Chen | 5 | 653 | 49.43 |
| To-Wei Chen | 6 | 158 | 13.96 |
| Liang-Gee Chen | 7 | 3637 | 383.22 |