Name
Abstract | ||
|---|---|---|
Complex image processing algorithms, when implemented on chip, require a significant amount of memory. Communication between the processing elements of an image processing system consumes most of the bandwidth of the system bus. This paper presents a novel architecture for a system on chip targeting image processing applications. Main focus is placed on optimizing the communication overhead between the image processing elements. Evaluation of this architecture is made in a custom FPGA platform and in ASIC implementation. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/RSP.2008.33 | IEEE International Workshop on Rapid System Prototyping |
Keywords | Field | DocType |
novel architecture,asic implementation,image processing application,efficient image,image processing element,novel system-on-chip architecture,custom fpga platform,system bus,complex image processing algorithm,image processing system,communication overhead,processing element,image processing,chip,field programmable gate arrays,machine vision,real time systems,bandwidth,computer architecture,system on a chip,application software,computer vision,fpga,prototypes,image sensors,system on chip,image processing algorithms | Architecture,Computer architecture,System on a chip,Computer science,Image processing,Field-programmable gate array,Application-specific integrated circuit,Bandwidth (signal processing),Computer hardware,Digital image processing,System bus,Embedded system | Conference |
ISSN | Citations | PageRank |
1074-6005 | 1 | 0.37 |
References | Authors | |
1 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| V. Mariatos | 1 | 7 | 1.82 |
| K. D. Adaos | 2 | 15 | 2.88 |
| G. P. Alexiou | 3 | 9 | 3.18 |