Name
Abstract | ||
|---|---|---|
We present GrÆStl, a combined hardware architecture for the Advanced Encryption Standard (AES) and Grøstl, one of the final round candidates of the SHA-3 hash competition. GrÆStl has been designed for low-resource devices implementing AES-128 (encryption and decryption) as well as Grøstl-256 (tweaked version). We applied several resource-sharing optimizations and based our design on an 8/16-bit datapath. As a feature, we aim for high flexibility by targeting both ASIC and FPGA platforms and do not include technology or platform-dependent components such as RAM macros, DSPs, or Block RAMs. Our ASIC implementation (fabricated in a 0.18μm CMOS process) needs only 16.5 kGEs and requires 742/1,025 clock cycles for encryption/decryption and 3,093 clock cycles for hashing one message block. On a Xilinx Spartan-3 FPGA, our design requires 956 logic slices and 302 logic slices on a Xilinx Virtex-6. Both stand-alone implementations of AES and Grøstl outperform existing FPGA solutions regarding low-area design by needing 79% and 50% less resources as compared to existing work. GrÆStl is the first combined AES and Grøstl implementation that has been fabricated as an ASIC. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1007/978-3-642-37288-9_12 | CARDIS |
Keywords | Field | DocType |
asic implementation,logic slice,stl implementation,xilinx spartan-3 fpga,xilinx virtex-6,combined aes,fpga solution,low-area design,fpga platform,clock cycle,fpga,aes,asic,embedded systems | Datapath,Advanced Encryption Standard,Computer science,FPGA prototype,Field-programmable gate array,Application-specific integrated circuit,Real-time computing,Grøstl,Encryption,Embedded system,Hardware architecture | Conference |
Citations | PageRank | References |
1 | 0.35 | 18 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Markus Pelnar | 1 | 17 | 1.09 |
| Michael Muehlberghuber | 2 | 42 | 4.85 |
| Michael Hutter | 3 | 345 | 25.26 |