Name
Title | ||
|---|---|---|
An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD |
Abstract | ||
|---|---|---|
This paper presents an approach of logic mapping into LUT-Array-Based PLD where Boolean functions in the form of the sum of generalized complex terms (SGCTs) can be mapped directly. While previous mapping approach requires predetermined variable ordering, our approach performs mapping and variable reordering simultaneously. For the purpose, we propose a directed acyclic graph based on the multiple valued decision diagram (MDD) and an algorithm to construct the graph. Our algorithm generates candidates of SGCT expressions for each node in a bottom-up manner and selects the variables in the current level by evaluating the sizes of SGCT expressions directly. Experimental results show that our approach reduces the number of terms maximum to 71 percent for the MCNC benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1093/ietfec/e88-a.4.907 | IEICE Transactions |
Keywords | Field | DocType |
boolean function,previous mapping approach,lut-array-based pld,variable ordering,variable reordering,bottom-up manner,sgct expression,logic mapping,acyclic graph,integrated approach,mcnc benchmark circuit,terms maximum | Logic synthesis,Boolean function,Discrete mathematics,Lookup table,Expression (mathematics),Algorithm,Theoretical computer science,Directed acyclic graph,Influence diagram,Electronic circuit,Mathematics,AND gate | Journal |
Volume | Issue | ISSN |
E88-A | 4 | 1745-1337 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomonori Izumi | 1 | 34 | 20.88 |
| Shin'Ichi Kouyama | 2 | 6 | 1.93 |
| Hiroyuki Ochi | 3 | 215 | 44.57 |
| Yukihiro Nakamura | 4 | 177 | 50.18 |