Name
Abstract | ||
|---|---|---|
The interpin skew among the data and the strobe signals of a source-synchronous parallel DRAM interface is compensated by a simple delay-locked loop, which reuses the circuitry of a normal input data path. With the interpin skew compensation, the printed circuit board traces of the data and the strobe signals are allowed to have unequal length. The prototype implemented in a 0.13-$\mu{\rm m}$ standard CMOS process shows that the interpin skew is reduced to be less than 26 ps for a 3.2-Gb/s/pin $\times 8$ parallel interface. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TVLSI.2012.2227853 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
delay locked loop,skew compensation technique,bit rate 3.2 gbit/s,cmos,source synchronous parallel dram interface,delay-locked loop (dll),parallel interface,source-synchronous parallel dram interface,dram chips,standard cmos process,strobe signals,interpin skew compensation,synchronous dram (sdram),printed circuit board trace,cmos memory circuits,size 0.13 mum | Dram,Data path,Computer science,Printed circuit board,Electronic engineering,Cmos process,Real-time computing,Skew,Source-synchronous,Parallel port,CAS latency | Journal |
Volume | Issue | ISSN |
21 | 11 | 1063-8210 |
Citations | PageRank | References |
1 | 0.36 | 1 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jang-Woo Lee | 1 | 5 | 2.29 |
| Hong-Jung Kim | 2 | 21 | 3.70 |
| Chun-Seok Jeong | 3 | 19 | 4.20 |
| Jae-Jin Lee | 4 | 27 | 8.69 |
| Changsik Yoo | 5 | 116 | 34.39 |