Name
Abstract | ||
|---|---|---|
We describe the application ESBC to perform the timing analysis of a combinatorial circuit. The circuit is described by formulas of Classical Logic and the delays of propagation of the signals in a gate are represented by a kind of valuation form semantics. ESBC computes the exact stabilization times at which the output signals stabilize. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1016/j.entcs.2005.08.004 | Electr. Notes Theor. Comput. Sci. |
Keywords | Field | DocType |
valuation form semantics,classical logic,output signal,application esbc,timing analysis,combinatorial circuit,exact stabilization time,intermediate logics,stabilization bound | Discrete mathematics,Computer science,Theoretical computer science,Static timing analysis,Classical logic,Semantics | Journal |
Volume | Issue | ISSN |
153 | 1 | Electronic Notes in Theoretical Computer Science |
Citations | PageRank | References |
2 | 0.40 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alessandro Avellone | 1 | 63 | 7.66 |
| Mauro Ferrari | 2 | 93 | 16.05 |
| Camillo Fiorentini | 3 | 121 | 21.00 |
| Guido Fiorino | 4 | 97 | 12.71 |
| Ugo Moscato | 5 | 138 | 16.17 |