Name
Abstract | ||
|---|---|---|
In this paper, we present a run-time task migration scheme for an adjustable/reconfigurable issue-slots very long instruction word (VLIW) multi-core processor. The processor has four 2-issue ρ-VEX VLIW cores that can be merged together to form larger issue-width cores. With a task migration scheme, a code running on a core can be shifted to a larger or a smaller issue-width core for increasing the performance or reducing the power consumption of the whole system, respectively. All the cores can be utilized in an efficient manner, as a core needed for a specific job can be freed at run-time by shifting its running code to another core. The task migration scheme is realized with the implementation of interrupts on the ρ-VEX cores. The design is implemented in a Xilinx Virtex-6 FPGA. With different benchmarks, we demonstrate that migrating a task running on a smaller issue-width core to a larger issue-width core at run-time results in a considerable performance gain (up to 3.6x). Similarly, gating off one, two, three, or four cores can reduce the dynamic power consumption of the whole system by 24%, 42%, 61%, or 81%, respectively. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1007/978-3-642-28365-9_9 | ARC |
Keywords | Field | DocType |
run-time result,vex vliw core,smaller issue-width core,larger issue-width core,dynamic power consumption,considerable performance gain,run-time task migration scheme,vex core,whole system,adjustable issue-slots,multi-core processor,task migration scheme,multi core,interrupts | Very long instruction word,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Dynamic demand,Code (cryptography),Multi-core processor,Power consumption,Embedded system | Conference |
Citations | PageRank | References |
0 | 0.34 | 17 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fakhar Anjam | 1 | 31 | 3.63 |
| Quan Kong | 2 | 11 | 4.04 |
| Roel Seedorf | 3 | 0 | 0.34 |
| Stephan Wong | 4 | 119 | 12.80 |