Name
Abstract | ||
|---|---|---|
This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1016/j.sysarc.2004.04.001 | Journal of Systems Architecture |
Keywords | Field | DocType |
variable data-completion processing time,synchronous pipelined design,single-pulse pipeline,fpga pipelined design,clocking technique,fpgas,fpga circuit,micropipeline,fpga device,synchronous design methodology,pipelined circuit,data-completion circuitry,clocking pipeline technique,pipelines,asynchronous-like pipeline operation,field programmable gate array,design methodology | Asynchronous communication,Pipeline transport,Computer science,Parallel computing,Field-programmable gate array,Clock tree,Real-time computing,Design methods,Electronic circuit,Embedded system,Power consumption | Journal |
Volume | Issue | ISSN |
50 | 11 | Journal of Systems Architecture |
Citations | PageRank | References |
4 | 0.51 | 9 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Oswaldo Cadenas | 1 | 14 | 5.38 |
| Graham Megson | 2 | 13 | 4.03 |