Name
Abstract | ||
|---|---|---|
This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that can extract computations from applications to put into the RFU. The results show that large instruction sequences can be created and extracted by these techniques. An average speedup of 2.6 is achieved over a set of benchmarks. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1145/329166.329187 | FPGA |
Keywords | Field | DocType |
mixed processor,average speedup,compilation technique,reconfigurable functional unit,fpga architecture,c compiler,large instruction sequence,sieving,functional unit,chip | Computer architecture,Computer science,Parallel computing,Field-programmable gate array,Public key cryptosystem,Real-time computing,Compiler,Fpga architecture,Speedup,Computation | Conference |
ISBN | Citations | PageRank |
1-58113-193-3 | 41 | 3.43 |
References | Authors | |
10 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhi Alex Ye | 1 | 176 | 12.73 |
| Nagaraj Shenoy | 2 | 72 | 6.49 |
| Prithviraj Baneijee | 3 | 41 | 3.43 |