Name
Abstract | ||
|---|---|---|
We explore the practical limits on throughput imposed by timing in a long, self-timed, circulating pipeline (ring). We consider models with both fixed and random delays and derive exact results for pipelines where these delays are fixed or exponentially distributed random variables. We also give relationships that provide upper and lower bounds on throughput for any pipeline where the delays are independent random variables. In each of these cases, we show that the asymptotic processor utilization is independent of the length of the pipeline; thus, linear speedup is achieved. We present conditions under which this utilization approaches 100%. |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1007/BF00935211 | VLSI Signal Processing |
Keywords | Field | DocType |
Storage Time,Independent Random Variable,Linear Speedup,Systolic Array,Clock Period | Pipeline transport,Mathematical optimization,Random variable,Upper and lower bounds,Computer science,Systolic array,Exponential distribution,Throughput,Sum of normally distributed random variables,Speedup | Journal |
Volume | Issue | Citations |
2 | 3 | 37 |
PageRank | References | Authors |
3.94 | 3 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mark R. Greenstreet | 1 | 494 | 63.18 |
| Kenneth Steiglitz | 2 | 1128 | 660.13 |