Name
Abstract | ||
|---|---|---|
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power optimization techniques are strongly applied during the development of modern Application Specific Instruction Set Processors (ASIPs). Electronic System Level design tools based on Architecture Description Languages (ADL) offer a significant reduction in design time and effort by automatically generating the software tool-suite as well as the Register Transfer Level (RTL) description of the processor. In this paper, the automation of power optimization in ADL-based RTL generation is addressed.Operand isolation is a well-known power optimization technique applicable at all stages of processor development. With increasing design complexitiy several efforts have been undertaken to automate operand isolation. In pipelined datapaths, where isolating signals are often implicitly available, the traditional RTL-based approach introduces unnecessary overhead. We propose an approach which extracts high-level structural information from the ADL representation and systematically uses the available control signals. Our experiments with state-of-the-art embedded processors show a significant power reduction (improvement in power efficiency). |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/DATE.2006.243993 | DATE |
Keywords | Field | DocType |
power efficiency,design complexitiy,low power optimization technique,design time,electronic system level design,low power consumption,well-known power optimization technique,power optimization,operand isolation,embedded processor,significant power reduction,application software,system on chip,application specific instruction set processor,high level synthesis,registers,architecture description language,power generation,electronic system level,data mining,low power electronics,automation,register transfer level,embedded systems,hardware description languages,instruction sets,embedded system | Power optimization,Instruction set,Computer science,Real-time computing,Register-transfer level,Low-power electronics,Hardware description language,Computer architecture,System on a chip,High-level synthesis,Operand,Parallel computing,Embedded system | Conference |
ISSN | ISBN | Citations |
1530-1591 | 3-9810801-0-6 | 5 |
PageRank | References | Authors |
0.48 | 13 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Chattopadhyay | 1 | 59 | 4.48 |
| B. Geukes | 2 | 5 | 0.48 |
| D. Kammler | 3 | 50 | 4.68 |
| E. M. Witte | 4 | 114 | 8.86 |
| O. Schliebusch | 5 | 9 | 0.88 |
| H. Ishebabi | 6 | 5 | 0.82 |
| R. Leupers | 7 | 286 | 21.71 |
| G. Ascheid | 8 | 230 | 57.65 |
| H. Meyr | 9 | 75 | 4.14 |