Paper Info
Title
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories
Abstract
3D stacked memory enables more off-chip DDR memories. Redesigning existing IPs to exploit the increased memory parallelism will be prohibitively costly. In our work, we propose a practical approach to exploit the increased bandwidth and reduced latency of multiple off-chip DDR memories while reusing existing IPs without modification. The proposed approach is based on two new concepts: transaction id renaming and distributed soft arbitration. We present two on-chip network components, request parallelizer and read data serializer, to realize the concepts. Experiments with synthetic test cases and an industrial strength DTV SoC design show that the proposed approach gives significant improvements in total execution cycle (21.6%) and average memory access latency (31.6%) in the DTV case with a small area overhead (30.1% in the on-chip network, and less than 1.4% in the entire chip).
Year
DOI
Venue
2008
10.1145/1391469.1391585
DAC
Keywords
Field
DocType
off-chip ddr memory,practical approach,increased bandwidth,average memory access latency,multiple off-chip ddr memory,memory access parallelization,existing ips,dtv case,dtv soc design show,increased memory parallelism,parallel processing,chip,arbitration,network on a chip,bandwidth,system on a chip,memory management,network on chip,testing,parallelization,out of order,digital tv,memory
Computer science,Latency (engineering),Electronic engineering,Real-time computing,Memory management,Out-of-order execution,System on a chip,Parallel computing,Network on a chip,Chip,Serializer,Exploit,Embedded system
Conference
ISSN
Citations 
PageRank 
0738-100X
13
0.79
References 
Authors
8
6
Name
Order
Citations
PageRank
Woo-Cheol Kwon130015.08
Sungjoo Yoo2139896.56
Sung-Min Hong315216.56
Byeong Min4335.60
Kyu-Myung Choi516714.80
Soo-Kwan Eo6777.35