Name
Abstract | ||
|---|---|---|
This paper presents a module that solves the square root by obtaining a number of more significant bits from a look-up table as an approximate root. A set of possible roots are then appended and squared for comparison to the original radicand, finely tuning the calculation. The module stops as soon as it finds an exact root, therefore not all entries take the same number of cycles, reducing the number of iterations required for full resolution. The proposed FPGA module overcomes a Xilinx's logiCORE IP in terms of resources utilization and in several cases latency due to its flexible structure configuration. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/elex.9.971 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
Square root, non-restoring algorithm, FPGA | Square (algebra),Computer science,Latency (engineering),Arithmetic,Field-programmable gate array,Fixed point,Square root | Journal |
Volume | Issue | ISSN |
9 | 11 | 1349-2543 |
Citations | PageRank | References |
3 | 0.42 | 5 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fernando Martín del Campo | 1 | 32 | 3.62 |
| Alicia Morales-Reyes | 2 | 70 | 11.55 |
| Roberto Perez-Andrade | 3 | 39 | 5.88 |
| René Cumplido | 4 | 171 | 29.56 |
| Aldo G. Orozco-Lugo | 5 | 119 | 13.72 |
| Claudia Feregrino | 6 | 56 | 5.98 |