Name
Abstract | ||
|---|---|---|
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90 nm 26 kb SRAM module is reduced from 550 mV to 220 mV. A novel error-tolerant architecture further reduces the minimum static-error-free VDD to 155 mV. With a 100 mV noise margin, a 255 mV standby VDD effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1 V VDD. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISQED.2008.4479693 | ISQED |
Keywords | Field | DocType |
ultra-low power standby operation,optimisation,maximum data retention voltage,low voltage,ultra-low standby power,voltage 155 mv,sram module,data retention voltage,variation,sram leakage power,sram chips,drv,low-power electronics,sram cell optimization techniques,voltage 100 mv,minimum static-error-free vdd,voltage 1 v,novel error-tolerant architecture,error tolerant,voltage 255 mv,sram cell optimization technique,integrated circuit design,leakage,low power,size 90 nm,sram,ecc,typical standby,error-tolerant sram design,standby vdd,low power electronics,sleep,error correction,circuits,degradation,voltage,design optimization | Standby power,Leakage (electronics),Computer science,Voltage,Electronic engineering,Static random-access memory,Real-time computing,Integrated circuit design,Low voltage,Noise margin,Low-power electronics | Conference |
ISBN | Citations | PageRank |
978-0-7695-3117-5 | 3 | 0.54 |
References | Authors | |
4 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Huifang Qin | 1 | 101 | 20.23 |
| Animesh Kumar | 2 | 133 | 23.95 |
| Kannan Ramchandran | 3 | 9401 | 1029.57 |
| Jan M. Rabaey | 4 | 4796 | 1049.96 |
| Prakash Ishwar | 5 | 951 | 67.13 |