Name
Abstract | ||
|---|---|---|
An all-digital coherent-like binary frequency shift keying (BFSK) demodulation based on the use of a multi-bit shift register, two multi-bit XOR gates and a mean value filter is presented. The demodulator is fabricated in SMIC 65-nm CMOS process with a die area of 0.015mm2. The demodulator consumes 1.44mW with 1.2V of voltage supply and 32MHz of sample clock. The measured bit error ratio (BER) performance is better than that of other non-coherent demodulators. The proposed demodulator exhibits better performance in terms of composite indicator compared to other demodulators. Another advantage of the all-digital demodulator defined using Verilog HDL is that it can also be implemented on Field Programmable Gate Array (FPGA) platform rapidly to recover FSK signals with different carrier frequencies and data rates. These results make the all-digital demodulator suitable for the application in communication and consumer electronics. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1016/j.mejo.2014.02.017 | Microelectronics Journal |
Keywords | Field | DocType |
Binary frequency shift keying (BFSK),Demodulation,Demodulator,All-digital,Coherent-like | Word clock,Demodulation,Shift register,Frequency-shift keying,Field-programmable gate array,XOR gate,Electronic engineering,Verilog,Engineering,Electrical engineering,Bit error rate | Journal |
Volume | Issue | ISSN |
45 | 6 | 0026-2692 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaopeng Liu | 1 | 0 | 0.34 |
| Yan Han | 2 | 12 | 1.77 |
| Xiaoxia Han | 3 | 14 | 3.39 |
| Mingyu Wang | 4 | 135 | 24.90 |