Name
Abstract | ||
|---|---|---|
Intellectual property (IP) block reuse is becoming the mainstream of System-on-Chip (SOC) design. However, the trade of IP blocks poses significant high security risks. Consequently IP protection becomes sensitive and urgent. In this paper, DesignMarker platform used for IP protection is proposed, which is based on watermarking technique. Both netlist-level watermarking module and layout-level watermarking module are integrated with this platform. Through this platform, watermarking message can be embedded into IP at netlist-level or layout-level with few overhead costs. What's more, the platform can be extended and improved with new watermarking modules. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISQED.2009.4810309 | ISQED |
Keywords | Field | DocType |
watermarking technique,block reuse,new watermarking module,ip protection,intellectual property,watermarking message,ip protection platform,designmarker platform,layout-level watermarking module,ip block,netlist-level watermarking module,authentication,data mining,system on chip,robustness,system on a chip,watermarking,security,netlist,microelectronics,algorithm design and analysis,packaging,layout,ip,transistors | Netlist,Digital watermarking,Algorithm design,Authentication,System on a chip,Computer science,Reuse,Computer network,Robustness (computer science),Intellectual property,Embedded system | Conference |
Citations | PageRank | References |
2 | 0.36 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yun Du | 1 | 2 | 0.36 |
| Yangshuo Ding | 2 | 2 | 0.36 |
| Yujie Chen | 3 | 10 | 5.41 |
| Zhiqiang Gao | 4 | 6 | 1.26 |