Name
Title | ||
|---|---|---|
ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation |
Abstract | ||
|---|---|---|
An important issue in register-transfer-level (RTL) hardwareverification is the ability to check specified functions and to determine the presence of an error. Code-level coverage is often used to measure the success in verification at this level. However, existing code-level coverage inaccurately estimates the verification result by considering only the excitations of functional blocks.While it may be impossible to achieve 100% correctness with code-coverage measure, checking excitation of functions and monitoring the effects at output ports can improve reliability of functional verification.Thispaper presents an RTL functional verification approach that evaluates the excitation-states of conditional expressions and propagates the excited information to output ports.The proposed approach with Verilog PLI-based implementation provide more meaningful cover age value that can measure the extent of functional verification in a very effective way duringlogic simulation. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/PRDC.2001.992696 | PRDC |
Keywords | Field | DocType |
hardware description languages,logic design,logic simulation,logic testing,code-level coverage,functional verification,hardware description language,hardware verification,logic simulation,register-transfer-level | Functional verification,Computer science,Intelligent verification,Correctness,Runtime verification,Logic simulation,Verilog,High-level verification,Computer engineering,Hardware description language | Conference |
ISBN | Citations | PageRank |
0-7695-1414-6 | 2 | 0.40 |
References | Authors | |
11 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Byeong Min | 1 | 33 | 5.60 |
| Gwan Choi | 2 | 369 | 56.66 |