Paper Info
Title
Software methodologies for VHDL code static analysis based on flow graphs
Abstract
At a high level of abstraction, the VHDL specification of the functionalities that a circuit shall perform is given by defining the behavioral model. The similarity with procedural programming languages suggested to tailor some software analysis techniques to VHDL behavioral description analysis. The paper presents sev- eral analyses of the code, based on data flows, aimed at identify- ing significant properties of the final circuit from the synthesis and testability points of view.
Year
DOI
Venue
1996
10.1109/EURDAC.1996.558236
EURO-DAC
Keywords
Field
DocType
VHDL code,flow graph,software methodology,static analysis
Testability,Procedural programming,Programming language,Computer science,Software analysis pattern,Behavioral modeling,Static analysis,Theoretical computer science,Software development process,VHDL,Hardware description language
Conference
ISBN
Citations 
PageRank 
0-8186-7573-X
0
0.34
References 
Authors
7
3
Name
Order
Citations
PageRank
D. Sciuto170.88
L. Baresi216013.28
Cristiana Bolchini326723.72