Name
Abstract | ||
|---|---|---|
In the semiconductor manufacturing, yield enhancement is an important issue. It is ideal to prevent all failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasures. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically recognize and classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/11552451_181 | KES (2) |
Keywords | Field | DocType |
data mining,automatic detection,facilitates yield enhancement,failure pattern,failure analysis,yield inhibitor,yield enhancement,failure pattern extraction,automatic method,composite lot level yield,overall yield,bit map,semiconductor manufacturing | Data mining,Computer science,Semiconductor device fabrication,Bitmap | Conference |
Volume | ISSN | ISBN |
3682 | 0302-9743 | 3-540-28895-3 |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Youngshin Han | 1 | 27 | 8.28 |
| Junghee Kim | 2 | 1 | 1.09 |
| Chil-Gee Lee | 3 | 47 | 16.85 |