A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOS - Citegraph

Paper Info

Title
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOS

Abstract
This paper presents an 8-b two-step subranging analog-to-digital (ADC) using interpolation, averaging, offset compensation, and pipelining techniques to accomplish an effective number of bits of 7.6 b at 125 MSample/s. The 0.13-/spl mu/m CMOS ADC occupies 0.09 mm/sup 2/ and consumes 21 mW.

Year	DOI	Venue
2004	10.1109/JSSC.2004.836235	IEEE Journal of Solid-State Circuits
Keywords	DocType	Volume
Switches,Voltage,Clocks,Pipeline processing,CMOS technology,Quantization,Energy consumption,Delay,Analog-digital conversion,CMOS process	Journal	39
Issue	ISSN	Citations
12	0018-9200	16
PageRank	References	Authors
3.05	14	10

Authors (10 rows)

Cited by (16 rows)

References (14 rows)

Name	Order	Citations	PageRank
J. Mulder	1	16	3.05
C. M. Ward	2	16	3.05
Chi-Hung Lin	3	217	34.67
D. Kruse	4	16	3.05
J. R. Westra	5	16	3.05
M. Lugthart	6	16	3.05
E. Arslan	7	31	5.99
R. J. van de Plassche	8	70	88.28
K. Bult	9	83	137.13
F. M. L. van der Goes	10	16	3.05

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