Name
Title | ||
|---|---|---|
Design of data buffer circuit in high-speed, high-resolution video image acquisition system on FPGA |
Abstract | ||
|---|---|---|
This paper introduces a logic circuit of data buffer between higher speed ADC and lower speed DSP. While allowing dropping some frames, the circuit also realizes effective image rescale and image buffer transfers frame by frame. The realization of this design initially solves the problem of the video capture system, which is limited by the resolution of the image, and enables DVR system to get high-speed access to large-resolution image. |
Year | Venue | Keywords |
|---|---|---|
2007 | IMECS 2007: INTERNATIONAL MULTICONFERENCE OF ENGINEERS AND COMPUTER SCIENTISTS, VOLS I AND II | FPGA,data buffer circuit,video image acquisition system,effective data transfer |
Field | DocType | ISSN |
Computer science,Field-programmable gate array,Data buffer,Computer hardware,Embedded system | Conference | 2078-0958 |
ISBN | Citations | PageRank |
978-988-98671-4-0 | 0 | 0.34 |
References | Authors | |
1 | 3 | |