Paper Info
Title
Efficient architecture/compiler co-exploration for ASIPs
Abstract
In this paper, we present an efficient exploration algorithm for architecture/compiler co-designs of application-specific instruction-set processors. The huge design space is spanned by processor architecture parameters as well as different compiler optimization strategies. The objective space is multi-dimensional including conflicting objectives such as hardware cost, execution time and code size. The goal of the presented exploration algorithm is to determine the set of Pareto-optimal designs and compiler settings for a given benchmark program.In a case study, while exploring Pareto-optimal designs for a given DSP benchmark program, we show that for a realistic architecture family, the huge search space may be reduced dramatically using proper techniques to prune search spaces that may not contain Pareto-optimal solutions. Finally, we analyse and present solutions on what is the best architecture for a mixture of benchmark programs, i.e., what are the best architecture/compiler co-designs to execute the DSPstone benchmark.
Year
DOI
Venue
2002
10.1145/581630.581635
CASES
Keywords
Field
DocType
pareto-optimal design,dspstone benchmark,efficient architecture,different compiler optimization strategy,best architecture,compiler co-designs,benchmark program,processor architecture parameter,compiler co-exploration,dsp benchmark program,compiler setting,realistic architecture family,application specific instruction set processor,compiler optimization,search space,processor architecture
Space-based architecture,Architecture,Computer architecture,Interprocedural optimization,Computer science,Compiler correctness,Parallel computing,Loop optimization,Optimizing compiler,Real-time computing,Compiler,Microarchitecture
Conference
ISBN
Citations 
PageRank 
1-58113-575-0
22
1.49
References 
Authors
11
4
Name
Order
Citations
PageRank
Dirk Fischer1221.49
Jürgen Teich22886273.54
Michael Thies38410.01
Ralph Weper4605.03