Paper Info
Title
Rethinking memory redundancy: Optimal bit cell repair for maximum-information storage
Abstract
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unlike the traditional memory repair that attempts to replace all failed bit cells by redundant columns and/or rows, we propose to repair the important bits (e.g., the most significant bit) only so that the information density (i.e., the number of information bits per unit area) is maximized. Towards this goal, an efficient statistical algorithm is derived to efficiently estimate the information density and then optimize the memory system for maximum-information storage. Our experimental results demonstrate that with a traditional 6-T SRAM cell designed in a commercial 45nm CMOS process, the proposed MIMS design can successfully operate at an extremely low power supply voltage (i.e., 0.6 V) and improve the signal-to-noise ratio (SNR) by more than 20 dB compared to the traditional SRAM design.
Year
DOI
Venue
2011
10.1145/2024724.2024800
DAC
Keywords
Field
DocType
cmos process,information storage,proposed mims design,nanoscale manufacturing technology,memory,size 45 nm,6-t sram cell,optimal bit cell repair,information density,failed bit cell,maximum-information memory system,sram design,sram chips,important bit,process variation,rethinking memory redundancy,redundancy,new bit cell repair,memory redundancy,integrated circuit,memory system,maximum-information storage,cmos memory circuits,information bit,maintenance engineering,signal to noise ratio
Most significant bit,Computer science,Signal-to-noise ratio,Real-time computing,Static random-access memory,Electronic engineering,Redundancy (engineering),Process variation,Integrated circuit,Maintenance engineering,Bit cell
Conference
ISSN
ISBN
Citations 
0738-100x
978-1-4503-0636-2
2
PageRank 
References 
Authors
0.38
11
1
Name
Order
Citations
PageRank
Xin Li126418.95