Name
Abstract | ||
|---|---|---|
Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, we present methods for accelerating switch-level simulation by mapping it onto general purpose parallel computers. Our target machines are medium-grain multiprocessors (shared memory or message passing machines) and we only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. We introduce efficient strategies for circuit partitioning as well as the corresponding simulation algorithms. In our approach, we try to minimize the total number of synchronizations between processors, as well as ensure portability and scalability. A preprocessor and simulator were implemented and good performance was obtained for a set of benchmarks. The problem of tight coupling between processors that evaluate a strongly connected component in the circuit in a distributed fashion is highlighted. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/EDAC.1991.206417 | EURO-DAC |
Keywords | Field | DocType |
Switch-level simulation,corresponding simulation algorithm,MOS circuit,design verification process,general purpose parallel computer,model parallel computation,Large Scale Integrated,efficient strategy,good performance,medium-grain multiprocessors,parallel switch-level simulation | Shared memory,Parallel algorithm,Computer science,Parallel computing,High-level synthesis,Theoretical computer science,Software portability,Strongly connected component,Very-large-scale integration,Message passing,Scalability | Conference |
ISBN | Citations | PageRank |
0-8186-2130-3 | 2 | 0.45 |
References | Authors | |
19 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. B. Mueller Thuns | 1 | 88 | 11.23 |
| D. G. Saab | 2 | 196 | 21.34 |
| J. Abraham | 3 | 4905 | 608.16 |