Paper Info
Title
Evaluation and improvements of programming models for the Intel SCC many-core processor
Abstract
Since the beginning of the multicore era, parallel processing has become prevalent across the board. On a traditional multicore system, a single operating system manages all cores and schedules threads and processes among them, inherently supported by hardware-implemented cache coherence protocols. However, a further growth of the number of cores per system implies an increasing chip complexity, especially with respect to the cache coherence protocols. Therefore, a very attractive alternative for future many-core systems is to waive the hardware-based cache coherency and to introduce a software-oriented message-passing based architecture instead: a so-called Cluster-on-Chip architecture. Intel's Single-chip Cloud Computer (SCC), a many-core research processor with 48 non-coherent memory-coupled cores, is a very recent example for such a Cluster-on-Chip architecture. The SCC can be configured to run one operating system instance per core by partitioning the shared main memory in a strict manner. However, it is also possible to access the shared main memory in an unsplit and concurrent manner, provided that the cache coherency is then ensured by software. In this paper, we detail our first experiences gained while developing low-level software for message-passing and shared-memory programming on the SCC. In doing so, we evaluate the potential of both programming models and we show how these models can be improved especially with respect to the SCC's many-core architecture.
Year
DOI
Venue
2011
10.1109/HPCSim.2011.5999870
HPCS
Keywords
Field
DocType
microcomputers,parallel processing,microprocessor chips,cache storage,low-level software,single-chip cloud computer,chip complexity,schedules threads,message-passing,cluster-on-chip architecture,non-cache-coherent shared-memory,many-core research processor,scc,shared main memory,hardware-based cache coherency,intel scc many-core processor,operating system,noncoherent memory-coupled cores,shared memory systems,programming models,rcce,hardware-implemented cache coherence protocols,mpi,message passing,cloud computing,software-oriented message-passing based architecture,multicore system,many-core processors,shared-memory programming,computer architecture,instruction sets,programming,protocols,cache coherence,chip,programming model,shared memory,bandwidth,single chip cloud computer
Programming paradigm,MESIF protocol,Instruction set,Computer science,Cache algorithms,Smart Cache,Multi-core processor,Operating system,Cache coherence,Single-chip Cloud Computer
Conference
ISBN
Citations 
PageRank 
978-1-61284-380-3
35
2.10
References 
Authors
3
4
Name
Order
Citations
PageRank
Carsten Clauss19312.35
Stefan Lankes215226.39
Pablo Reble3606.32
Thomas Bemmerl422741.61