Name
Title | ||
|---|---|---|
A new survivor memory management method in Viterbi decoders: trace-delete method and its implementation |
Abstract | ||
|---|---|---|
The well known methods for survivor path storage and decoding are the register-exchange method (REM) and the trace-back method (TBM). The REM is conceptually simple, but it is not appropriate for VLSI implementation because it requires large power consumption and large chip area. The TBM is the preferred method in the VLSI implementation of Viterbi decoders (VD) having large constraint length and high performance. However, the TBM requires last-in-first-out (LIFO) buffer and has to use multiple read operations for high speed operation. This multiple operation results in complex control logic. In this paper, we propose a new survivor memory management method called trace-delete method (TDM) and realize this algorithm in hardware (H/W) for VLSI implementation and we compare the TDM with the TBM in terms of latency, the number of memory elements, and the requirements of control logic. The main advantage of the proposed method can be found as short latency and less requirements on additional control logic. Especially, if we combine the TDM with block interleaving the implementation is even simpler than the TBM. The method is studied with particular relevance to HDTV |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/ICASSP.1996.550578 | ICASSP |
Keywords | Field | DocType |
large chip area,integrated memory circuits,complex control logic,video signal processing,hdtv,latency,register-exchange method,viterbi decoding,trace-delete method,trace-back method,digital signal processing chips,storage management chips,block interleaving,implementation,new survivor memory management,vlsi implementation,vlsi,viterbi decoder,tdm,memory element numbers,additional control logic,preferred method,high definition television,control logic,viterbi decoders,television receivers,survivor memory management method,memory management,viterbi algorithm,decoding,time division multiplexing,hardware,multiplication operator,very large scale integration,chip,logic | Mathematical optimization,Computer science,Parallel computing,FIFO and LIFO accounting,Viterbi decoder,Memory management,Control logic,Decoding methods,Computer hardware,Very-large-scale integration,Viterbi algorithm,Interleaving | Conference |
Volume | ISSN | ISBN |
6 | 1520-6149 | 0-7803-3192-3 |
Citations | PageRank | References |
1 | 0.40 | 2 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sukjin Jung | 1 | 2 | 0.79 |
| Myeong-Hwan Lee | 2 | 2 | 1.33 |
| Hyung-Jin Choi | 3 | 264 | 40.12 |