Name
Abstract | ||
|---|---|---|
In chip multiprocessors (CMPs), multiple cores compete for shared resources such as on-chip caches and off-chip pin bandwidth. Stride-based hardware prefetching increases demand for these resources, causing contention that can degrade performance (up to 35% for one of our benchmarks). In this paper, we first show that cache and link (off-chip interconnect) compression can increase the effective cache capacity (thereby reducing off-chip misses) and increase the effective off-chip bandwidth (reducing contention). On an 8-processor CMP with no prefetching, compression improves performance by up to 18% for commercial workloads. Second, we propose a simple adaptive prefetching mechanism that uses cache compression's extra tags to detect useless and harmful prefetches. Furthermore, in the central result of this paper, we show that compression and prefetching interact in a strong positive way, resulting in combined performance improvement of 10-51% for seven of our eight workloads. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/HPCA.2007.346200 | HPCA |
Keywords | Field | DocType |
on-chip cache,stride-based hardware,combined performance improvement,effective off-chip bandwidth,cache compression,chip multiprocessors,effective cache capacity,8-processor cmp,commercial workloads,prefetching interact,off-chip pin bandwidth,data compression,system on chip | Compression (physics),System on a chip,Cache,Computer science,Parallel computing,Chip,Bandwidth (signal processing),Interconnection,Data compression,Embedded system,Performance improvement | Conference |
ISSN | ISBN | Citations |
1530-0897 | 1-4244-0804-0 | 26 |
PageRank | References | Authors |
0.99 | 38 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alaa R. Alameldeen | 1 | 1672 | 80.06 |
| David A. Wood | 2 | 6058 | 617.11 |