Name
Abstract | ||
|---|---|---|
System-on-chip design is facing increasing challenges in its integration, global wiring delay and power dissipation. Interconnection network technology has the advantage over conventional bus technology in its scalability; on the other hand, asynchronous circuit design technology may offer power saving and tackle the clock-skew problem. Chip designers are thus turning their attention to network-on-chip solutions. Packet-switches play a key role in interconnection networks and this paper focuses on their implementation as asynchronous circuits. The results of experiments run to evaluate several aspects of the routing switch implementation are presented |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ACSD.2006.1 | ACSD |
Keywords | Field | DocType |
packet switching,interconnection network technology,clock-skew problem,integrated circuit interconnections,routing switch implementation,network routing,synchronous data flow graphs,power dissipation,embedded data flow application,asynchronous packet-switching,networks-on-chip,application mapping,integrated logic circuits,global wiring delay,logic design,integrated circuit design,single processor,system-on-chip design,throughput analysis,asynchronous circuits,asynchronous circuit design technology,system-on-chip integration,useful tool,multiprocessing context,network-on-chip,bus technology,chip,clock skew,system on a chip,switches,system on chip,asynchronous circuit,network on chip,scalability | Logic synthesis,Asynchronous communication,System on a chip,Computer science,Network on a chip,Real-time computing,Integrated circuit design,Packet switching,Interconnection,Embedded system,Scalability | Conference |
ISSN | ISBN | Citations |
1550-4808 | 0-7695-2556-3 | 0 |
PageRank | References | Authors |
0.34 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jun Xu | 1 | 0 | 0.34 |
| Reza Sotudeh | 2 | 41 | 8.69 |
| Mark B. Josephs | 3 | 302 | 35.24 |