Name
Title | ||
|---|---|---|
A 90-nm Low-Power 32-kB Embedded SRAM With Gate Leakage Suppression Circuit for Mobile Applications |
Abstract | ||
|---|---|---|
In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local dc level control (LDLC) for SRAM cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits... |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/JSSC.2004.825235 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Random access memory,Gate leakage,Leakage current,CMOS technology,Voltage,Dielectric materials,Standby generators,Level control,Driver circuits,Temperature | Journal | 39 |
Issue | ISSN | Citations |
4 | 0018-9200 | 11 |
PageRank | References | Authors |
4.18 | 5 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Koji Nii | 1 | 223 | 44.78 |
| Y. Tsukamoto | 2 | 39 | 10.46 |
| Tomoaki Yoshizawa | 3 | 15 | 4.67 |
| Susumu Imaoka | 4 | 53 | 11.87 |
| Y. Yamagami | 5 | 27 | 6.11 |
| T. Suzuki | 6 | 11 | 4.18 |
| A. Shibayama | 7 | 43 | 19.79 |
| H. Makino | 8 | 15 | 5.28 |
| S. Iwade | 9 | 11 | 4.18 |