Name
Abstract | ||
|---|---|---|
An image segmentation algorithm, based on Pulse-Coupled Neural Networks, was implemented in silicon. We aimed at simplifying
neuron hardware implementation while maintaining segmentation efficiency. Some algorithmic tricks have then been added, improving
the results. The main components of the underlying neuron architecture are a single 8 bits register, a simple incrementer,
and some glue logic. A prototype, using a data flow architecture, implementing a 64x64 neuron array, and based on a 0.2 Μm
CMOS SOI technology, will be released in 1998. A 64x64 segmentation is expected in less than 50 Μs.
|
Year | DOI | Venue |
|---|---|---|
1998 | 10.1007/BFb0057630 | ICES |
Keywords | Field | DocType |
image segmentation,neural integrated circuit,integrated circuit,data flow | Dataflow architecture,Adaptive system,Simulation,Segmentation,Computer science,Field-programmable gate array,Glue logic,Image segmentation,Artificial neural network,Computer hardware,Integrated circuit,Distributed computing | Conference |
Volume | ISSN | ISBN |
1478 | 0302-9743 | 3-540-64954-9 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jean-Luc Rebourg | 1 | 0 | 0.34 |
| Jean-Denis Muller | 2 | 3 | 1.82 |
| Manuel Samuelides | 3 | 67 | 11.71 |