Name
Abstract | ||
|---|---|---|
Modern chip multiprocessors (CMPs) employ large L2 caches to reduce the performance gap between processors and off-chip memory. However, as the size of an L2 cache increases, its leakage power consumption also becomes a major contributor to the total power dissipation. Managing the leakage power of L2 caches, therefore, is an important issue in realizing low-power CMPs. In CMPs with private L2 caches, each processor makes a copy of the data in its local cache in order to access the data faster, which is called replication. In this paper, we propose a novel leakage management technique that dynamically turns off replications in private L2 caches for leakage power reduction by exploiting two key observations: 1) the cost of an extra cache miss due to the turned-off replication is small because the same cache block exists in another on-chip cache and 2) turning off the replication incurs no extra cache miss if it is invalidated by other processors in order to maintain cache coherence. Since blindly turning off the frequently accessed replications can degrade performance, the proposed technique dynamically controls the number of turned-off replications. The proposed technique can be implemented by slightly modifying the MESI protocol with a new turned-off shared (TOS) coherence state. The TOS state indicates that the corresponding block is shared by other caches but turned off. Experiments on a four-processor CMP with private L2 caches show that the proposed technique reduces the energy consumption of the L2 caches and the main memory by 19.4% on average, with less than 1% performance loss over the existing cache leakage management technique. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TVLSI.2012.2220791 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
leakage power management,private l2 caches,l2 cache leakage,low-power cmp,microprocessor chips,power dissipation,cache storage,leakage currents,on-chip cache,extra cache miss,cache coherence,leakage power reduction,four-processor cmp,tos coherence state,cache leakage management technique,low-power electronics,leakage power consumption,turned-off shared coherence state,replication,turned-off replications,mesi protocol,replicated cache blocks,performance loss,off-chip memory,chip multiprocessors (cmps),chip multiprocessors,data faster,low power electronics | Cache pollution,Computer science,Cache,MESI protocol,Parallel computing,Real-time computing,Cache algorithms,Cache coloring,Bus sniffing,Smart Cache,Cache coherence | Journal |
Volume | Issue | ISSN |
21 | 10 | 1063-8210 |
Citations | PageRank | References |
4 | 0.44 | 19 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyunhee Kim | 1 | 34 | 5.51 |
| Jung Ho Ahn | 2 | 2657 | 122.11 |
| Jihong Kim | 3 | 1336 | 104.37 |