Name
Abstract | ||
|---|---|---|
We present a modeling technique for assessing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Since the magnitude of the noise problem is a function of the relative proximity of noisy and sensitive devices, design aids are required which can incorporate the switching noise effects at the post-layout phase of design verification. In our approach, SPICE-compatible lumped element RC substrate macromodels are efficiently generated from the circuit layout using a geometric construct called the Voronoi tessellation. The new models retain the accuracy of previously reported models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing larger circuits. The node count reduction is realized by deriving a model topology which automatically adapts itself to the local densities of substrate features associated with the noise coupling. Our strategy has been verified using detailed 2-D device simulation, and successfully applied to some mixed-A/D circuit examples |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/43.476576 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
CMOS integrated circuits,computational geometry,integrated circuit modelling,integrated circuit noise,mixed analogue-digital integrated circuits,2D device simulation,CMOS mixed-signal circuits,SPICE-compatible lumped element RC substrate macromodels,Voronoi tessellation,design,geometric construct,integrated circuit substrate coupling models,layout,switching noise,topology | Journal | 14 |
Issue | ISSN | Citations |
12 | 0278-0070 | 27 |
PageRank | References | Authors |
5.69 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| I. L. Wemple | 1 | 27 | 5.69 |
| A. T. Yang | 2 | 145 | 35.28 |