Name
Abstract | ||
|---|---|---|
System and circuit design can be considered as planning problems, where resources are deployed in time and space to meet a given goal. Recent and continuing developments in the size of SAT problems and other AR problems that can be solved with off-the-shelf tools leads us to consider their direct use in system design. In this paper we start to tackle the design of small hardware subsystems and the generation of glue logic between systems by asking a SAT solver to generate the programming bit stream for a ctional gate array. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/RSP.2004.13 | IEEE International Workshop on Rapid System Prototyping |
Keywords | Field | DocType |
logic design,functional programming,system design,formal specification,sat solver,gate array,formal specifications,field programmable gate arrays,integrated circuit design,circuit design,logic programming,planning,job design,computability,hardware | Logic synthesis,Computer architecture,Programming language,Computer science,Boolean satisfiability problem,Glue logic,Systems design,Circuit design,Field-programmable gate array,Formal specification,Logic programming | Conference |
ISSN | ISBN | Citations |
1074-6005 | 0-7695-2159-2 | 0 |
PageRank | References | Authors |
0.34 | 1 | 1 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David J. Greaves | 1 | 124 | 30.48 |