Name
Title | ||
|---|---|---|
A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches |
Abstract | ||
|---|---|---|
Power dissipation becomes an important issue in modern microprocessors such as chip multiprocessors (CMPs). Especially as the process technology advances below 90nm, the leakage power consumption becomes dominant in the total power dissipation, thus reducing the leakage power consumption is an important design goal for low-power CMPs. In particular, since most CMPs employ a large L2 cache, reducing the leakage power consumption of the L2 cache is critical in realizing low-power CMPs. In this paper, we propose a leakage-aware on-chip L2 cache organization called LACS. The proposed LACS, like the existing RACS organization, is based on a private L2 cache organization with an inter-L2 cache sharing support. However, unlike the RACS organization, which determines a peer L2 cache block for an inter-L2 cache sharing based on the reusability of the evicted L2 block and performance implications of peer L2 cache blocks, the LACS organization considers both the performance and leakage. The LACS organization reduces the leakage power consumption significantly over the leakage-oblivious RACS organization while achieving a similar performance gain over a private L2 cache organization. Experimental results show that the proposed LACS technique reduces the energy consumption by 23.6% and improves the energy delay product by 18.6% on average over the existing RACS scheme. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1509084.1509089 | Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture |
Keywords | DocType | Citations |
l2 block,lacs organization,chip multiprocessors,leakage-aware cache sharing technique,leakage power consumption,inter-l2 cache,reusability,low-power cmps,l2 cache management,leakage energy,inter-l2 cache sharing support,low-power chip multi-processors,l2 cache block,l2 cache organization,l2 cache,racs organization,chip,power dissipation | Conference | 0 |
PageRank | References | Authors |
0.34 | 11 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyunhee Kim | 1 | 34 | 5.51 |
| Sungjun Youn | 2 | 1 | 0.69 |
| Jihong Kim | 3 | 1336 | 104.37 |