Name
Title | ||
|---|---|---|
Design and performance of a coherent cache for parallel logic programming architectures |
Abstract | ||
|---|---|---|
This paper describes the design and performance of a tightly-coupled shared-memory coherent cache optimized for the execution of parallel logic programming architectures. The cache utilizes a copy-back write-allocation protocol having five states and a hardware lock mechanism. Optimizations for logic programming are introduced in four software-controlled memory access commands: direct-write, exclusive-read, read-purge, and read-invalidate. In this paper we describe these operations and present simulated measurements showing their performance advantage for an architecture of the committed-choice language KL1. The cache optimizations also improve the performance of non-committed-choice languages, such as OR-parallel Prolog. A version of the cache design described here is currently being implemented for ICOT's Parallel Inference Machine (PIM). |
Year | DOI | Venue |
|---|---|---|
1989 | 10.1145/74926.74929 | international symposium on computer architecture |
Keywords | Field | DocType |
cache optimizations,parallel inference machine,or-parallel prolog,cache design,parallel logic programming architecture,logic programming,performance advantage,tightly-coupled shared-memory coherent cache,copy-back write-allocation protocol,committed-choice language kl1,shared memory,bandwidth,concurrent computing,writing,design optimization,hardware,computer architecture | Cache-oblivious algorithm,Computer architecture,Cache invalidation,Cache pollution,MESIF protocol,Computer science,Cache,Parallel computing,Real-time computing,Cache algorithms,Cache coloring,Smart Cache | Conference |
Volume | Issue | ISSN |
17 | 3 | 0163-5964 |
ISBN | Citations | PageRank |
0-89791-319-1 | 7 | 0.69 |
References | Authors | |
15 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Atsuhiro Goto | 1 | 95 | 29.29 |
| A. Matsumoto | 2 | 7 | 0.69 |
| Evan Tick | 3 | 141 | 27.07 |