Name
Abstract | ||
|---|---|---|
In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region, utilizes this current, minimizing power consumption in low-frequency systems. This paper proposes two architectures for implementing Flip-Flop cells, designed to operate in the subthreshold region. Both cells integrate a Gate-Diffusion Input (GDI) multiplexer in their designs to minimize area and capacitance. Timing parameters of the Flip-Flops are calculated and techniques for improving the timing characteristics are proposed. The proposed designs are simulated in a standard 90nm process achieving a power dissipation of 8.4nW in a typical corner at VDD=300mV with a delay of 51.7nsec. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISCAS.2009.5118070 | ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 |
Keywords | Field | DocType |
digital circuits,propagation delay,logic gates,vlsi,low frequency,transistors,very large scale integration,leakage current,power dissipation,cmos logic,multiplexing,cmos technology | Digital electronics,Logic gate,Propagation delay,Leakage (electronics),Computer science,CMOS,Multiplexer,Electronic engineering,Subthreshold conduction,Electrical engineering,Low-power electronics | Conference |
Citations | PageRank | References |
1 | 0.38 | 6 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sagi Fisher | 1 | 11 | 1.09 |
| Adam Teman | 2 | 129 | 19.12 |
| Dmitry Vaysman | 3 | 1 | 0.38 |
| Alexander Gertsman | 4 | 1 | 0.38 |
| Orly Yadid-Pecht | 5 | 230 | 35.79 |
| Alexander Fish | 6 | 64 | 7.48 |