Title
A fully complementary and fully differential self-biased asynchronous CMOS comparator.
Abstract
This paper presents a novel CMOS asynchronous voltage comparator topology composed of a preamplifier cascaded by the positive feedback latch. The proposed circuit is fully differential and possesses desired properties like purely capacitive input impedance with rail-to-rail output swing, low noise and offset, etc. Furthermore, the comparator is also completely self-biased embedding the negative feedback in the biasing loop which makes it highly resistant to process, supply voltage and temperature variations. The design and optimization methodologies are discussed as well. Since the comparator delivers high operating speeds under relatively low power consumption, it is suitable for use in tomorrow's SoC data transceivers and converters.
Year
DOI
Venue
2012
10.1109/ICECS.2012.6463674
ICECS
Keywords
Field
DocType
CMOS integrated circuits,asynchronous circuits,comparators (circuits),feedback,network topology,optimisation,power supplies to apparatus,preamplifiers,system-on-chip,transceivers,SoC data converters,SoC data transceivers,biasing loop,cascaded preamplifier,differential circuit,fully differential self-biased asynchronous CMOS voltage comparator topology,high operating speeds,low power consumption,negative feedback,optimization methodologies,positive feedback latch,rail-to-rail output swing,self-biased embedding,temperature variations,voltage supply
Comparator,Preamplifier,Computer science,Voltage,Negative feedback,Capacitive sensing,CMOS,Converters,Electronic engineering,Comparator applications
Conference
Citations 
PageRank 
References 
0
0.34
4
Authors
2
Name
Order
Citations
PageRank
Vladimir Milovanovic113.67
Horst Zimmermann22915.60