Name
Title | ||
|---|---|---|
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization |
Abstract | ||
|---|---|---|
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay and energy requirement of driving the result tags across the associatively-addressed issue queue accounts for a significant percentage of the scheduler's overhead and also limits the design scalability. We propose two schemes to reduce the power consumption and the delays of the wakeup logic. Our first scheme - instruction packing - shares the associative part of an issue queue entry between two instructions, each with at most one non-ready source. As a result, the number of entries in the issue queue (and, hence, the length of the tag buses) can be reduced by a factor of two with almost no impact on the IPCs, because most instructions either enter the pipeline with at least one of their source operands ready, or do not make use of two source registers to begin with. Our second scheme - tag memoization - avoids driving the upper portion of the tags, if those bits did not change their values from what was driven on the same tag bus during the most recent broadcast. While instruction packing results in the reduced length of the tag buses, tag memoization reduced the number of tag lines that need to be driven. We evaluate our designs using detailed microarchitectural simulations of the SPEC 2000 benchmarks and the SPICE simulations of the issue queue layouts. Modern superscalar processors use out of order execution to exploit instruction level parallelism. The dynamic scheduling engine employed in such processors often uses associative logic embedded into the issue queue entries to wakeup instructions that are awaiting a result. This is accomplished by storing the address of the source registers within the issue queue entries and using the comparators that match the stored source register values against the address of the result that is driven on tag bus lines. A significant amount of energy dissipation results as the destination register address is driven on the tag busses. Energy dissipation occurs when the tag bus lines |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1007/11574859_2 | PACS |
Keywords | Field | DocType |
out of order execution,power dissipation,dynamic scheduling,energy dissipation,instruction scheduling | Broadcasting,Instruction scheduling,Spice,Computer science,Queue,Operand,Parallel computing,Spec#,Memoization,Embedded system,Scalability | Conference |
Volume | ISSN | ISBN |
3471 | 0302-9743 | 3-540-29790-1 |
Citations | PageRank | References |
24 | 1.80 | 28 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joseph J. Sharkey | 1 | 124 | 8.44 |
| Dmitry Ponomarev | 2 | 893 | 56.45 |
| Kanad Ghose | 3 | 1220 | 113.50 |
| Oguz Ergin | 4 | 424 | 25.84 |