Paper Info
Title
An efficient linearity test for on-chip high speed ADC and DAC using loop-back
Abstract
Our method extracts the linearity of on-chip high speed data converters with minimum area overhead. With a loop-back setup in the presence of noise, differential nonlinearities (DNLs) and integral nonlinearities (INLs) of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) can be extracted by the proposed method. Our approach exploits the fact that the loop-back output distribution due to noise is distorted by nonlinearities of the ADC, but not by those of the DAC. We first fully characterize the ADC in the loop-back system, exclusive of the DAC. Then, the DAC is characterized using the extracted nonlinearities of the ADC. Numerical simulation shows a maximum error of less than ±0.1 LSB for the ADC and the DAC.
Year
DOI
Venue
2004
10.1145/988952.989031
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
integral nonlinearities,minimum area overhead,maximum error,digital-to-analog converter,on-chip high speed,loop-back system,loop-back setup,loop-back output distribution,efficient linearity test,analog-to-digital converter,differential nonlinearities,chip,numerical simulation,linearity
Flight dynamics (spacecraft),Loopback,Integral nonlinearity,Differential nonlinearity,Control theory,Computer science,Linearity,Converters,Electronic engineering,Successive approximation ADC,Least significant bit
Conference
ISBN
Citations 
PageRank 
1-58113-853-9
5
0.70
References 
Authors
7
3
Name
Order
Citations
PageRank
Ji Hwan (Paul) Chun1162.39
Hak-soo Yu2283.37
J. Abraham34905608.16