Name
Abstract | ||
|---|---|---|
The manual creation of specialized hardware infrastructures for complex multi-purpose systems is error-prone and time-consuming. Moreover, lots of effort is required to define an optimized and heterogeneous components library. To tackle these issues, we propose a novel design flow based on the Dataflow Process Networks Model of Computation. In particular, we have combined the operation of two state of the art tools, the Multi-Dataflow Composer and the Open RVC-CAL Compiler, handling respectively the automatic mapping of are configurable multi-purpose substrate and the high level synthesis of hardware components. Our approach guarantees runtime efficiency and on-chip area saving both on FPGAs and ASICs. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6271969 | 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) |
Keywords | Field | DocType |
hardware,application specific integrated circuits,field programmable gate arrays,high level synthesis,asic,fpga | Computer architecture,Computer science,High-level synthesis,Field-programmable gate array,Design flow,Application-specific integrated circuit,Compiler,Dataflow,Model of computation,Embedded system,Reconfigurable computing | Conference |
ISSN | Citations | PageRank |
0271-4302 | 5 | 0.46 |
References | Authors | |
6 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jean-François Nezan | 1 | 144 | 18.39 |
| Nicolas Siret | 2 | 5 | 0.46 |
| Matthieu Wipliez | 3 | 241 | 18.36 |
| Francesca Palumbo | 4 | 67 | 18.37 |
| Luigi Raffo | 5 | 265 | 38.89 |