Title
512-Mb PROM with a three-dimensional array of diode/antifuse memory cells
Abstract
A 512-Mb one-time-programmable memory is described, which uses a transistorless two-terminal memory cell containing an antifuse and a diode. Cells are fabricated in polycrystalline silicon, stacked vertically in eight layers above a 0.25-mum CMOS substrate. One-time programming is performed by applying a high voltage across the cell terminals, which ruptures the antifuse and permanently encodes a logic 0. Unruptured antifuses encode a logic 1. Cells are arranged in 8-Mb tiles, 1 K rows by 1 K columns by 8 bits high. The die contains 72 such tiles: 64 tiles for data and eight tiles for error-correcting code bits. Wordline and bitline decoders, bias circuits, and sense amplifiers are built in the CMOS substrate directly beneath the memory tiles, improving die efficiency. The device supports a generic standard HAND flash interface and operates from a single 3.3-V supply.
Year
DOI
Venue
2003
10.1109/JSSC.2003.818147
IEEE Journal of Solid-state Circuits
Keywords
DocType
Volume
CMOS memory circuits,PROM,VLSI,elemental semiconductors,memory architecture,silicon,0.25 micron,3.3 V,3D diode/antifuse memory cell array,512 Mbit,CMOS substrate,PROM,Si,bias circuits,bitline decoders,error-correcting code,generic standard NAND flash interface,one-time-programmable memory,polycrystalline Si,sense amplifiers,three-dimensional array,transistorless two-terminal memory cell,vertically stacked layers,wordline decoders
Journal
38
Issue
ISSN
Citations 
11
0018-9200
8
PageRank 
References 
Authors
2.19
1
14
Name
Order
Citations
PageRank
M. Johnson182.53
A. Al-Shamma2285.05
D. Bosch311213.44
M. Crowley482.19
M. Farmwald582.19
L. Fasoli682.19
A. Ilkbahar782.19
B. Kleveland882.19
T. Lee982.19
Tz-yi Liu10285.05
Quang Nguyen1182.19
R. Scheuerlein1282.19
K. So1382.19
T. Thorp1482.19